Static RAM is used as high-speed semiconductor memory in various equipment, and is incorporated into various system LSIs. SRAM does not lose stored data the way DRAM does, and SRAM does not require periodic refresh operations. But a memory cell of SRAM normally has a latch circuit comprising a pair of CMOS inverters with inputs and outputs cross-connected, and one pair of access transistors, for a total of six transistors. Hence in order to increase storage capacity, transistor miniaturization is necessary.
SRAM has a plurality of word lines which select memory cells in the row direction, and a plurality of bit line pairs which select memory cells in the column direction. By driving a word line, access transistors are made to conduct, and storage node pairs of the latch circuits in memory cells are connected to bit line pairs. Then, read operations and write operations can be performed via the bit line pairs.
In a write operation, from a state in which the bit line pair is precharged, one line of the selected bit line pair is discharged to generate a potential difference across the bit line pair, and then the word line is driven to cause the access transistors to be conducting, so that the bit line pair potential difference is used to write data to the memory cell. Hence a write operation entails an operation of pulling down a precharged bit line to L level, so that a large amount of power is consumed.
In a read operation, from a state in which the bit line pair is precharged, the word line is driven to cause the access transistors to be conducting, a bit line is driven to L level from one storage node of the memory cell latch circuit, and the potential difference generated across the bit line pair is detected. Hence in a read operation, the word line is driven to connect the bit line pair to the memory cell latch circuit via the access transistors, and so the memory cell operating margin must have at least a fixed value or higher in order that the memory cell latch circuit is not inverted due to the effects of external noise and similar.
In Japanese Patent Laid-open No. 2005-25863, two-port SRAM is disclosed. The SRAM disclosed has a pair of CMOS inverters, an access transistor pair which connects the pair of CMOS inverters to a bit line pair, a word line pair which controls conduction of the respective transistors of the access transistor pair, and a pair of read transistors which respectively read the output nodes of the pair of CMOS transistors; the lines of the word line pair control conduction of the respective transistors of the read transistor pair.